1. Field of the Invention
This invention relates to computer systems and, more particularly, to arrangements for manipulating numbers in a unique number format used in a matrix arithmetic section of an extremely fast graphics accelerator.
2. History of the Prior Art
In designing computer systems the emphasis is constantly on making such systems faster so that they may do more work. Computers with graphics displays are able to do more work than are computers which present only numbers and text material. Unfortunately, the presentation of graphics by a computer requires a great deal of the processing power of that system. For example, the presentation of a single frame of graphical material on the output display of a fairly standard-sized workstation requires that information regarding approximately one thousand pixels in a horizontal direction and approximately one thousand pixels in a vertical direction be stored, approximately one million pixels for each frame to be displayed. In a color system, each of those pixels contains eight or more bits of digital information defining each pixel. Consequently, approximately eight million bits of information needs to be handled and stored for each frame to be presented on the output display. Since frames are repeated thirty times a second on the output display, the total amount of information required to be presented at the output display simply to cause the display itself to operate is a very large number. The simple matter of dealing with such a large amount of information in order to present a graphics output occupies a substantial amount of the time available for a central processing unit (CPU) and may substantially slow the operation of even the fastest of such processors.
For this reason, it has become common for computer systems to include graphics accelerators capable of assisting the central processing unit in its operations by taking over some portion of the data processing function relating to the display of graphics. This offloading of some of the graphics processing functions from the central processing unit to a graphics accelerator can substantially increase the speed with which any particular computer system is able to process graphics information.
Attempts are being made to design very fast graphics accelerators. One of the major functions which may be accomplished by a graphics accelerator is to handle the matrix arithmetic necessary for moving graphics images about on the computer output display. Such matrix operations are necessary in handling both two and three-dimensional graphical figures in order to rotate, translate, scale, and otherwise manipulate the particular graphics figures to be displayed on the computer output display. A graphics accelerator can be very useful in accomplishing these operations because it can relieve the central processing unit of the need to serially recompute various vertices of the figures to be manipulated with each manipulation of the figure to be displayed. A graphics accelerator may accomplish the many operations necessary by means of hardware manipulation of the data and greatly speed the operation of the computer system using such a system.
However, a major problem still remains in obtaining extremely rapid operations. This problem derives from the need of a graphics accelerator to manipulate data in a plurality of different number formats. For example, information handled by a central processing unit normally appears in an integer format and must appear in that format when utilized by an output display because a display does not deal in fractions of pixels. On the other hand, many manipulations with very large numbers used in scientific processing require the use of a floating point format. Such numbers must be dealt with in presenting graphics for such scientific projects. It is clear that such floating point type numbers must ultimately be translated into the integer format for presentation on a computer output display. Additionally, other formats such as that described by the acronym FRACT may be especially useful in manipulating a particular type of graphics display. All of such formats are different, and in prior art systems numbers must be constantly translated between one and another format.
In prior art computer systems, the central processing unit (CPU) has been called upon to accomplish most number translations. Thus, although a floating point number may be processed by use of a floating point co-processor, it must ultimately be converted by a processor of the system into integer format so that it may be used in displaying a particular graphical output on a computer output display. The translation of numbers between different number formats by a processor is handled serially, is very time consuming, and substantially slows the operation of any computer system.
To speed the operation of a graphics accelerator, a new number format has been devised for internal use by matrix transformation circuitry. Copending U.S. patent application Ser. No. 07/407,928, entitled NUMBER CONVERSION APPARATUS, Priem and Malachowsky, filed on even date herewith, describeds a circuit for translating numbers in integer, floating point, and FRACT formats to and from numbers stated in this new format (called Modulo 256 with multiple tap points number format, hereinafter "Modulo 256"). There is still required, however, the unique circuitry and processes for handling the matrix transformation operations in the Modulo 256 number format in which all internal manipulation may be accomplished.